The present disclosure relates to semiconductor memory devices, and specifically to a method for shielding a main bit line for a reference cell.
In semiconductor memory devices such as flash memory devices, a bit line and a word line are selected to specify a memory cell in a memory cell array, and the memory cell can thus be accessed. The bit line includes a main bit line and a sub bit line, the main bit line is connected to one end of the sub bit line via a selection transistor, and the other end of the sub bit line is connected to the memory cell. When data is read from a memory cell, a sense amplifier compares a current value or a voltage value of the specified memory cell with a current value or a voltage value of a reference cell serving as a reference to determine whether the data is “0” or “1.”
In an virtual ground-type memory cell array, when a memory cell adjacent to a memory cell which is to be accessed is in an erased state, a leakage current is caused. In contrast, when the memory cell adjacent to the memory cell which is to be accessed is in a written state, the leakage current can be prevented by charges which have been charged in the adjacent memory cell (see FIG. 1 of International Patent Publication No. WO 2005/109442). Thus, a dummy cell is disposed at an end of the memory cell array, and the dummy cell is set to the written state, so that it is possible to prevent the leakage current of the memory cell. International Patent Publication No. WO 2005/109442 has proposed a method for preventing a leakage current of a reference cell by disposing a dummy cell at an end of a reference cell array, and setting the dummy cell to the written state (see FIG. 5 and FIG. 6 of International Patent Publication No. WO 2005/109442). Japanese Patent Publication No. 2002-100196 is cited for reference.